PURPOSE: To maintain an excellent quality of low power consumption, and to enable logic at high speed by inserting a high resistance layer among each electrode and forming an electric field by the diffusion potential of a junction in the high resistance layer and a channel low impurity-density region.

CONSTITUTION: N layers 131, 13 having desired impurity density and thickness are grown continuously to a P+ Si substrate 11 in an epitaxial manner. An oxide film 16 is formed to the surface of the N grown layer 13, the oxide film is etched selectively, and a P type impurity (such as B) is diffused selectively into regions 14 as gate regions. The oxide films 16 are removed, and N type epitaxial grown layers 13', 132 are formed again. The impurity concentration of the grown layer 13' is made slightly higher in order to inhibit the auto-doping of the impurity from the gate P+ regions 14, and the gate P+ regions also extend to the grown layer 13' side through auto-doping and heat treatment on growth. An N+ region 12 is obtained through N+ diffusion or N+ epitaxial growth, one parts of the gate regions 14 is exposed to the surface by selectively etching Si, while Al is evaporated, and each electrode is formed.