PURPOSE: To replace a faulty storage area with a spare storage area within the chip of a flash EEPROM and to prolong the service life of the chip.
CONSTITUTION: A memory cell array is provided with 256 blocks constituting a data area and spare blocks having the same sizes respectively. When the generation of errors on the blocks of the data area is detected based on a verification result by a verifying circuit 122, an address for specifying the error block is registered in a replacement address table 15. Then, after this, when an address for specifying the error block is inputted from the outside, this address and the address of the error block registered in the replacement address table 15 are compared by a block selection control circuit 16. In this case, when adress values are made coincident, the error block and the the spare block are replaced, instead of the error block the spare block is selected and accessed.