Title:
【発明の名称】半導体装置の製造方法
Document Type and Number:
Japanese Patent JP3315345
Kind Code:
B2
Abstract:
A fabrication process includes a step of providing a substrate to be fabricated. A multi-layer antireflective layer is then formed on the substrate. A patterned resist having a thickness less than 850 nanometers is formed on the multi-layer antireflective layer and the substrate is fabricated using the patterned resist as a mask.
Inventors:
Tsukasa Azuma
Norihisa Oiwa
Tetsuro Matsuda
David M. Dobtzynski
Katsuya Okumura
Norihisa Oiwa
Tetsuro Matsuda
David M. Dobtzynski
Katsuya Okumura
Application Number:
JP13317397A
Publication Date:
August 19, 2002
Filing Date:
May 23, 1997
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
Toshiba Corporation
Toshiba Corporation
International Classes:
G03F7/11; G03F7/09; H01L21/027; (IPC1-7): H01L21/027; G03F7/11
Domestic Patent References:
| JP60117723A | ||||
| JP5226244A | ||||
| JP258221A | ||||
| JP5114559A | ||||
| JP7263309A |
Attorney, Agent or Firm:
Takehiko Suzue (3 outside)