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Patent Searching and Data


Title:
CACHE MEMORY SYNCHRONIZATION SYSTEM
Document Type and Number:
Japanese Patent JPH06103166
Kind Code:
A
Abstract:

PURPOSE: To improve the hit rate of a cache memory in a load decentralized OS.

CONSTITUTION: In a function decentralization system of a cache memory secures the coincidence of contents between the cache memory and a main storage of a multiprocessor system using a memory sharing system for each processor based on the state display of each cache memory. When a transfer request of a memory block is produced by a writing mistake of a cache memory, a bus request is produced for transfer of the memory block and also to simultaneously and forcibly read the memory block to be transferred to the processor that produced a memory block transfer request into the next practicable processor. This processor displays a state where the memory blocks to be transferred to the processors having the block transfer requests are simultaneously and forcibly read.


Inventors:
AGO SHINJI
Application Number:
JP16785393A
Publication Date:
April 15, 1994
Filing Date:
July 07, 1993
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F12/08; G06F15/16; G06F15/163; G06F15/177; (IPC1-7): G06F12/08; G06F15/16
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)