Title:
【発明の名称】データ回線のクロック遅延調整と回線断の監視回路
Document Type and Number:
Japanese Patent JP2979669
Kind Code:
B2
Abstract:
PURPOSE:To easily investigate the cause of a fault when generating line disconnection by recognizing it according to the output of a disconnection detecting circuit just before delay and the output of the disconnection detecting circuit just after switching whether the position of the line disconnection is before or behind a delay circuit. CONSTITUTION:When an out-of-phase state is generated at the clock and data of inputs, a switching system circuit 2 applies prescribed delay, which is successively enlarged, to an input clock CK0 of a delay circuit 1 and selects one of plural output lines for outputting the inputs according to a switching signal from the outside. Then, the phase of the output clock is made coincident with the phase of the data and outputted. When line disconnection is generated, a disconnection detecting circuit 3-1 just before delay detects the interruption of the input data just before the circuit 1, and a disconnection detecting circuit 3-2 just after switching detects the interruption of the data just after the switching system circuit 2. Thus, according to the output of the circuit 3-1 just before delay and the output of the circuit 3-2 just after switching, it can be recognized whether the position of the line disconnection is before or behind the circuit 1.
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Inventors:
KATO AKIRA
Application Number:
JP2431891A
Publication Date:
November 15, 1999
Filing Date:
February 19, 1991
Export Citation:
Assignee:
FUJITSU KK
International Classes:
H04L7/00; H04L25/02; H04L69/40; (IPC1-7): H04L25/02; H04L7/00; H04L29/14
Domestic Patent References:
| JP1282946A |
Attorney, Agent or Firm:
Teiichi