Title:
【発明の名称】マルチプレクサ回路
Document Type and Number:
Japanese Patent JP3016354
Kind Code:
B2
Abstract:
For time division multiplexing N bit-parallel circuit input signals at a high bit rate such as higher than 2.4 Gb/s, where N represents a predetermined integer greater than one, a multiplexer circuit comprises an N-stage shift register (11) for shifting a signal pulse through first to N-th dual output D F/F's (11(1)-11(N)) to produce N master and slave output signals as N stage output signals, N two-input NAND gates (15(1)-15(N)) supplied with the N bit parallel circuit input signals and the N master output signals to produce N gate output signals, an N-input NAND gate (17) multiplexing the N gate output signals into a single gate output signal, and a retiming D F/F (19) for retiming the single gate output signal into a bit-serial circuit output signal. The N slave output signals are delivered respectively to the dual output D F/F's of next stages. Each master output signal is produced by a slave input transfer gate (37) in each dual output F/F comprising master and slave latches master-slave connected together. Preferably, the signal pulse is a negative going pulse. NOR gates may be used instead of the NAND gates.
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Inventors:
Masakazu Kurisu
Application Number:
JP1485396A
Publication Date:
March 06, 2000
Filing Date:
January 31, 1996
Export Citation:
Assignee:
NEC
International Classes:
H03M9/00; H04J3/04; (IPC1-7): H03M9/00
Domestic Patent References:
| JP389719A | ||||
| JP4258012A | ||||
| JP4227122A | ||||
| JP258921A | ||||
| JP260325A | ||||
| JP61258525A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)