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Patent Searching and Data


Title:
PRINTED WIRING BOARD
Document Type and Number:
Japanese Patent JPH0637515
Kind Code:
A
Abstract:

PURPOSE: To control a partial characteristic impedance by providing conductive dead-end holes which are arranged in corner parts of a logic signal circuit to match the characteristic impedance of the logic signal circuit.

CONSTITUTION: After pair layers 9 are formed, outer layers of single-sided plates 10 are arranged in first and sixth layers, and they are laminated with a prepreg 4 between them, and a prescribed wiring board 5 is obtained by heating and pressure. Conductive dead-end holes 3a are arranged in corner parts of the logic signal circuit of the inner layer to eliminate mismatching of the characteristic impedance, thus obtaining the printed board having a uniform characteristic. The size, the number, and the depth of conductive dead- end holes 3a are changed to change a capacity C to the logic signal circuit, and as the result, the characteristic impedance can be controlled based on relations of characteristic impedance Z0=(L/C)1/2.


Inventors:
AKIMOTO YUTAKA
Application Number:
JP19125592A
Publication Date:
February 10, 1994
Filing Date:
July 20, 1992
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01P1/02; H01P3/08; H01P5/00; H01P5/02; H01P11/00; H05K3/46; (IPC1-7): H01P5/02; H01P1/02; H01P3/08; H01P11/00; H05K3/46
Domestic Patent References:
JPS525254B11977-02-10
JPH03261202A1991-11-21
JPS5531373B21980-08-18
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)