PURPOSE: To compensate the erroneous reading of data due to the shift or missing of a horizontal pulse by generating a reading clock pulse at a position corresponding to each bit location of a digital signal.

CONSTITUTION: A signal Sv is inserted with digital signals SD1, SD2, which are formed respectively with a 5-bit data. When said signal Sv is applied to a synchronous separator circuit 1 and a data slicer circuit 2, the reading clock pulse CP1 is outputted from a clock generating circuit 5. The pulse CP1 consists of a pulse corresponding to each said bit. Moreover, a phase shift detecting pulse CP2 is outputted from a clock generating circuit 9. The pulse CP2 is formed by three advanced detecting pulses inserted before a leading bit and 7 delayed detecting pusles. The pulses CP1, CP2 are applied to a shift register 6 through an OR gate 10 so as to read the data comprising the signals SD1 and SD2 correctly.