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Title:
CONTROLLING SYSTEM FOR MEMORY DATA PREFETCH
Document Type and Number:
Japanese Patent JPS5835627
Kind Code:
A
Abstract:

PURPOSE: To stop the prefetch of data from a main memory, by setting the inverted output of a D type FF to zero when a memory address counter designates an address beyond the last memory address of the main memory in the course of memory data prefetch.

CONSTITUTION: Each time one memory cycle is terminated, a memory request signal MREQ is outputted from an AND gate 74. In this state, assuming that the memory address exceeds the boundary of the memory block and exceeds the block on the boundary and becomes an integral multiple of physical address 128, the 18th bit A18 of the memory address is switched from "0" to "1", and a D type FF 73 is set in accordance with switching of the bit A18 of the memory address from "0" to "1", and the Q' output becomes "0". Thus, the output of the memory request signal MREQ is inhibited, and as the result, the prefetch memory data from the main memory is stopped.


Inventors:
KOBAYASHI YOSHIYUKI
YAMAGAMI YOSHIHIKO
KIHARA JIYUNICHI
Application Number:
JP13349381A
Publication Date:
March 02, 1983
Filing Date:
August 26, 1981
Export Citation:
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Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
G06F3/06; G06F5/06; G06F5/14; G06F9/38; G06F13/12; G06F13/28; (IPC1-7): G06F3/00; G06F5/06; G06F13/00
Attorney, Agent or Firm:
Takehiko Suzue



 
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