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Patent Searching and Data


Title:
TIME DIVISION MULTIPLEXER
Document Type and Number:
Japanese Patent JPS6052141
Kind Code:
A
Abstract:

PURPOSE: To attain supervision of high transmission quality by performing a reception state signal transmission of a high-speed digital signal of an opposite device and pseudo random code transmission of bit error rate estimation of the high-speed digital signal with one signal to improve the utilizing efficiency of the bit error rate estimation.

CONSTITUTION: The high-speed digital signal dh' received by a supervising circuit 107 of a reception signal is supervised always and 1 or 0 is added to an AND gate 201 depending on the presence of the signal dh'. Further, a pseudo random code prs is generated from a pseudo random code generator 101 and a logical product is outputted from the gate 201. An output of the gate 201 and low-speed digital signal from terminals 102, 103 are outputted while being subjected to time division multiplex at a multiplex circuit 104. Moreover, a separation circuit 108 separates the signal dh' into a low-speed digital signal, an erroneous bit of the pseudo random code is counted by an erroneous bit counter circuit 109 and a discriminating circuit 202 discriminates the state of the signal. Then the utilizing efficiency of the high speed digital signal is increased.


Inventors:
NISHITANI KAZUO
Application Number:
JP16077883A
Publication Date:
March 25, 1985
Filing Date:
September 01, 1983
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
H04J3/14; (IPC1-7): H04J3/14
Attorney, Agent or Firm:
Uchihara Shin