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Patent Searching and Data


Title:
MATRIX BOARD AND CONTINUITY TEST METHOD
Document Type and Number:
Japanese Patent JPH0638250
Kind Code:
A
Abstract:

PURPOSE: To detect incorrect separation between intermediate layers and to detect wrong intermediate layer insertion by leading out the intermediate layer of a matrix board to an end face of a printed circuit board and using an extracted point as a test terminal for the continuity test.

CONSTITUTION: A U shaped pattern is provided on intermediate layer patterns L2-L5, the one sides are arranged on a line in the longitudinal direction, and the other sides are arranged in a line obliquely, they are led to the side face of a printed circuit board and a leadout point is used for a test terminal TP. Then the terminal TP arranged in the longitudinal direction of the patterns L2, L3 is short-circuited by a content of the continuity tester, and the continuity test is implemented from the terminals TP of the patterns L2, L3 arranged obliquely. Similarly the terminals TP of the patterns L4, L5 in the longitudinal direction are short-circuited by a content of the continuity tester, and the continuity test is implemented from the terminals TP of the patterns L4, L5 arranged obliquely. Thus, use of an intermediate layer whose distance differs and a wrong intermediate layer inserted are easily detected.


Inventors:
KANEKO YOSHIMI
Application Number:
JP18558592A
Publication Date:
February 10, 1994
Filing Date:
July 14, 1992
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04Q1/14; H05K1/11; H05K3/46; H05K1/00; H05K1/02; (IPC1-7): H04Q1/14; H05K1/11; H05K3/46
Attorney, Agent or Firm:
Teiichi