Title:
【発明の名称】半導体集積回路の信頼性検証装置及び検証方法並びに検証プログラムを格納した記憶媒体
Document Type and Number:
Japanese Patent JP2996214
Kind Code:
B2
Abstract:
A semiconductor integrated circuit reliability verification device for detecting any portion of design that may cause circuit malfunction due to the effects of switching noise, comprises a partial circuit network detecting part for detecting, based on a transistor-level net list for the circuit to be verified, information concerning partial circuit networks that form part of a circuit to be verified, a maximum resistance calculating part for calculating, based on the information concerning the partial circuit network, the maximum resistance that occurs while the channel connected component is operating, a gate capacitance calculating part for calculating, based on the information concerning the partial circuit network, the total gate capacitance for the portions but the inverter of a driven circuit, and an error judging part for calculating the value of evaluation function, based on the value of maximum resistance and the total gate capacitance, and judging whether or not the calculated value is in violation of the design criteria.
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Inventors:
Shuzo Murai
Application Number:
JP23657897A
Publication Date:
December 27, 1999
Filing Date:
August 18, 1997
Export Citation:
Assignee:
NEC
International Classes:
H01L21/82; G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP1096762A | ||||
| JP3208177A |
Attorney, Agent or Firm:
Masao Matsumoto