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Patent Searching and Data


Title:
ADDING AND SUBTRACTING CIRCUIT
Document Type and Number:
Japanese Patent JPS5852747
Kind Code:
A
Abstract:

PURPOSE: To increase an arithmetic speed by supplying the borrow output of an arithmetic logical operating means to a borrow flip-flop, and thus storing the borrow generation.

CONSTITUTION: The absolute value of an augend or minuend is set in an absolute value register 2 through a data bus 1, and the absolute value of an adden or subtrahend is set in an absolute value register 3. If the sign of the augend or minuend set in a sign register 5 is positive and the sign of the addend or subtrahend set in a sign register 6 is positive when an addition or subrraction instruction is generated, an EXOR circuit 7 commands an adder 4 to execute an addition instruction 0. Then, the absolute value of the augend or minuend is added to the absolute value of the addend or subtrahend by the output S of the adder 4 to input the sum to an accumulator 10, and a borrow output B0 of 0 is outputted to a borrow FF11; and an EXOR circuit 8 outputs 0 to a sign register 9 for the arithmetic result.


Inventors:
TAKI MASAHARU
Application Number:
JP15170681A
Publication Date:
March 29, 1983
Filing Date:
September 25, 1981
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F7/505; G06F7/50; (IPC1-7): G06F7/50
Domestic Patent References:
JPS5647841A1981-04-30
Attorney, Agent or Firm:
Uchihara Shin