PURPOSE: To prevent malfunction due to an abnormal current and deterioration and a breakdown of an element, by providing a means of setting the source potential of a writing load transistor (TR) for writing data in a floating gate MOS memory to a prescribed level.

CONSTITUTION: At a memory part 11, plural memory cells MC each consisting of an MOSFETTF of floating gate structure are arrayed in a matrix. This memory is equipped with a row decoder 12, a column decoder 13, a column direction selecting circuit 14, inverters I1WI3 for successively inverting a data input signal DIN, a writing load FETT1, and a writing control FETTW1, and the source of the FETT1 and the common output terminal of the column direction selecting circuit 14 are connected to a sense amplifier. Through the potential setting part 15 consisting of a writing control FETTW2, a potential setting FETT2, and a switch FETT3, the source potential of the FETT1 is set to a prescribed potential prior to data writing to a memory cell MC, preventing the generation of an abnormal current.