PURPOSE: To obtain a gate wiring with high accuracy by laminating and forming a first polycrystalline Si wiring layer and a polycrystalline Si layer containing a large amount of P on a semiconductor substrate, reducing the area of the polycrystalline Si layer containing P through etching, applying a second polycrystalline Si wiring layer on the whole surface containing the polycrystalline Si layer and removing the polycrystalline Si layer containing P together with the second layer on the polycrystalline Si layer containing P when when the polycrystalline Si gate wiring is formed on the substrate.

CONSTITUTION: A first polycrystalline Si wiring layer 13, an SiO2 layer 14, a polycrystalline Si layer 15 containing a large amount of P and an Si3N4 layer 16 are laminated and formed on an Si substrate 11 through a gate SiO2 film 12. A laminate is divided while the area of the layer 15 is reduced through anisotropic dry etching as a resist film 17 is used as a mask. The film 17 and the layer 16 are removed, the film 12 is renewed to a film 18 while the exposed side surface of the layer 15 is coated, and a second polycrystalline Si wiring layer 20 is applied on the whole surface and the layer 15 is removed together with the layer 20 appplied on the layer 15.