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Patent Searching and Data


Title:
POWER LINE SUPERPOSED COMMUNICATION DEVICE
Document Type and Number:
Japanese Patent JPS5950627
Kind Code:
A
Abstract:

PURPOSE: To eliminate the effect on communication level even if a load impedance is fluctuated, by using the 1st and the 2nd envelope detecting circuit having a relatively large and small time constant.

CONSTITUTION: When a signal of FSK modulation is applied to an input terminal 1, the signal is amplified at amplifiers 2, 3, 4 and transmitted to an indoor distribution network from an AC plug via capacitors C4, C5 for power frequency signal cut and a tank circuit 5. The noise component synchronized with a frequency twice the power frequency in the signal is detected at an envelope detecting circuit 8 and a high frequency signal is eliminated. If there exists fluctuation in an output signal due to the fluctuation in the power impedance, the signal level transmitted to the indoor distribution network is fed back via the tank circuit 5 and the high frequency component is eliminated at an envelope detecting circuit 9.


Inventors:
KAWAI MAKOTO
Application Number:
JP16051982A
Publication Date:
March 23, 1984
Filing Date:
September 14, 1982
Export Citation:
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Assignee:
OMRON TATEISI ELECTRONICS CO
International Classes:
H04B3/08; H04B3/04; H04B3/54; H04L25/02; H04L27/12; (IPC1-7): H04B3/04; H04L25/02; H04L27/12
Domestic Patent References:
JPS4998905A1974-09-19
Attorney, Agent or Firm:
Nakamura Shigenobu