PURPOSE: To easily specify the address of a coprocessor instruction generating an exception by saving contents to be stored by a storage means in an exception processing saving area in a main storage at the time of informing exception detection from the coprocessor to the master processor.

CONSTITUTION: This exception processing system is provided with a storage means 3 for storing the address of an instruction, the 1st control means 11 for storing the address including a coprocessor instruction extracted by the master processor 1 in the storage means 3 and the 2nd control means 12 for saving the contents of the means 3 to the exception processing saving area 41 of the main storage device 4 when exception detection is informed from the coprocessor 2 to the master processor 1. Even when exceptional operation is generated in the coprocessor instruction and the master processor 1 has already executed processing the coprocessor instruction to be the cause of the exception, the address including the coprocessor instruction can be known from the contents of the area 41.