PURPOSE: To remarkably improve a gate delay time by providing a buried layer having a conductivity type opposed to that of the operation layer to a semi-insulated substrate provided between a high concentration layer and operation layer.

CONSTITUTION: A high concentration layer 4 consisting of the n+ layer having a high carrier concentration in the same conductivity type as the operation layer 2 is formed by ion implantation with a gate electrode 3 used as the mask. The p type buried layer 5 having the conductivity type opposed to that of the operation layer 2 is also formed by the ion implantation. Since the p type buried layer 5 is embedded at the lower end part of the source and drain of operation layer 2, sufficiently small amount of electrons are implanted to a semi-insulated substrate 1 from the high concentration layer 4 and therefore short channel effect is difficult to occur. Therefore, a threshold voltage is not lowered even when the gate length is made shorter than the existing one. As a result, a mutual conductance can be set large and a gate delay time can also be shortened.