Title:
BINARY INFORMATION TRANSMITTING SYSTEM
Document Type and Number:
Japanese Patent JPS605651
Kind Code:
A
Abstract:
A monolithically integratable transmission system for binary information has at least one address source which is connected to at least one address sink via an address bus. The address sink is respectively allocated to a register means connected to a data bus. A clock generator generates a first clock signal and a non-overlapping, phase-shifted second clock signal. The address bus and the data bus are precharged during the first clock signal and access of an addressed register means to the data bus occurs during the second clock signal. In the time span between the two clock signals, the address bus is charged with the address signals by discharging.
Inventors:
GERUHARUTO GAIGAA
MIHIAERU SHIYUTORAAFUNAA
MIHIAERU SHIYUTORAAFUNAA
Application Number:
JP11066084A
Publication Date:
January 12, 1985
Filing Date:
May 30, 1984
Export Citation:
Assignee:
SIEMENS AG
International Classes:
G06F13/40; G06F13/42; H04L25/02; (IPC1-7): H04L25/02; G06F13/20; H04L11/00
Attorney, Agent or Firm:
Tomimura Kiyoshi
Next Patent: SIGNAL DETECTING CIRCUIT