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Title:
CHANNEL INTERRUPTION CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS6041154
Kind Code:
A
Abstract:

PURPOSE: To execute prior processing of a designated I/O and to prevent competition with other programs by providing a channel device with an I/O designation register, a matching circuit and a matching validity designating register.

CONSTITUTION: When an end report from a designated I/O 9-1 is inputted to a data channel 4, the end report is stored in a channel status storing area 8 through the matching circuit 3 and an interruption information FF6 is set up. Consequently, a central control processor 5 detects the end report from the I/O 9-1. If a termination report is generated from an I/O 9-n other than the designated one, the circuit 3 is unmatched, the termination report is not stored in the storage area 8 and the FF6 also is not set up. Therefore, the processor 5 sends a waiting signal to the I/O 9-n to wait the end report. Consequently, the designated I/O 9-1 can be processed with priority and competition with other programs can be prevented.


Inventors:
SETO HAJIME
OOTSU YOSHIKATSU
OOMA TOSHIO
Application Number:
JP14939483A
Publication Date:
March 04, 1985
Filing Date:
August 16, 1983
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F13/12; (IPC1-7): G06F13/12
Attorney, Agent or Firm:
Kugoro Tamamushi



 
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