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Title:
INTERFACE OF DATA PROCESSING SYSTEM
Document Type and Number:
Japanese Patent JPS6019247
Kind Code:
A
Abstract:

PURPOSE: To facilitate an easy fault analysis by recording simultaneously the data obtained when an error arises, by both devices connected to each other.

CONSTITUTION: When an error is detected by an error detecting circuit 20 at the side of an interface 10, a driver 30 is actuated to transmit an error detection signal to an interface 11 via an error detection line 12. At the same time, the transmission of a timing signal is stopped to suppress the actuation of an output interaction control circuit 24. A signal line group 14 is frozen; while a memory 26 is actuated to store the signal states of output and input interaction signal line groups 46 and 47. Then a receiver 50 is actuated at the side of the interface 11 whether the error detection signal is received, and the timing 66 of an output interaction timing circuit 75 is stopped via an error interaction control circuit 70. Thus an output conversation circuit 74 is suppressed, and an output interaction signal line group 64 is set under a state obtained in a fault detection signal mode. Thus a signal line group 15 is frozen. Then a memory 72 stores the signal states of the group 64 and an input interaction signal group 63.


Inventors:
SAKAMOTO AKIO
Application Number:
JP12634083A
Publication Date:
January 31, 1985
Filing Date:
July 12, 1983
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G06F11/34; G06F11/07; G06F13/00; (IPC1-7): G06F11/34; G06F3/00; G06F13/00
Attorney, Agent or Firm:
Naotaka Ide



 
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