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Title:
CONTROL PROCESSING SYSTEM TO PLURAL INPUT AND OUTPUT DEVICES
Document Type and Number:
Japanese Patent JPS5816323
Kind Code:
A
Abstract:

PURPOSE: To decrease the processing time, by shunting temporarily the head address of the control table under reference when an interruption arises.

CONSTITUTION: An RAM3 connected to a CPU includes a communication controlling table area and a stack area. The communication controlling table area includes a control table which stores various data to the communication controlling circuits 4 and an area to be used as a pointer register. When an interruption signal is fed to the CPU1, the contents of the pointer register is shunted to the stack area. Then the head address of the controlling table is stored in the pointer register. When the interruption signal comes to an end, the data shunted in the stack area is sent back to the cntents of the pointer register. In such a way, the processing time can be decreased.


Inventors:
CHIWAKI RIYUUICHI
HAMADA YUKINORI
Application Number:
JP11415281A
Publication Date:
January 31, 1983
Filing Date:
July 20, 1981
Export Citation:
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Assignee:
OMRON TATEISI ELECTRONICS CO
International Classes:
G06F13/10; G06F9/46; G06F9/48; G06F13/24; (IPC1-7): G06F3/00; G06F9/46
Attorney, Agent or Firm:
Kenji Ushiku



 
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