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Patent Searching and Data


Title:
SHORTENING SYSTEM FOR BRANCH INSTRUCTION
Document Type and Number:
Japanese Patent JPS5854449
Kind Code:
A
Abstract:

PURPOSE: To minimize the memory in a table required for shortening a branch instruction as possible by setting up a new entry on an idle entry or an entry of which address distance exceeds its tolerance.

CONSTITUTION: When a label L1 of an addess to which a branch instruction is to be jumped is not yet recorded in a label table, the address (a) of the branch istruction is recorded and left in the label table. If the definition of the label L1 is found at an address (c) and the difference between the address (c) and the address (a) of the branch instruction satisfies (c-a)≤127, an operation converting the branch instruction into a short type one is performed and the flag pit of an entry in which the address of the branch instruction is recorded is turned to "0". An entry having the flag pit "0" and an entry in which the difference between definition address or a reference address and a present value of an address counter exceeds 128 are idle entries.


Inventors:
TAZAKI HIDEAKI
Application Number:
JP15328581A
Publication Date:
March 31, 1983
Filing Date:
September 28, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F9/32; G06F9/45; (IPC1-7): G06F9/44
Attorney, Agent or Firm:
Yutaka Morita