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Patent Searching and Data


Title:
PROGRAM TIMER
Document Type and Number:
Japanese Patent JPS599583
Kind Code:
A
Abstract:

PURPOSE: To attain to miniaturize the apparatus and to reduce the cost thereof, by a method wherein the memory content of an electric power reset memory means and the setting state of an indicating means are determined and specific load is driven only at the time of an output setting state to unnecessitate output send-out inhibiting circuit.

CONSTITUTION: When a mode selecting switch 7 is turned ON and a confirmation reset mode is selected and set, it is decided whether the power failure flag 9C in RAM 9 is brought to 1 or not and, because an electric power reset state is meant if said flag 9C is 1, CPU 1 performs the starting treatment of an electric power reset state display circuit to carry out light ON-and-OFF display in a display part 11 of a day of the week. An operator confirms the electric power reset state by this electric power reset display and decides the approval of output send-out in consideration with the load state during power failure or a power failure time to operate the output key of a keyboard 14. Therefore, it can be prevented that a program is carried out automatically and directly after electric power is recovered and erroroneous operation can be eliminated.


Inventors:
IGA MASAAKI
Application Number:
JP11957182A
Publication Date:
January 18, 1984
Filing Date:
July 08, 1982
Export Citation:
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Assignee:
OMRON TATEISI ELECTRONICS CO
International Classes:
G04G15/00; (IPC1-7): G04G15/00
Attorney, Agent or Firm:
Hisao Komori