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Patent Searching and Data


Title:
DIAGNOSTIC SYSTEM
Document Type and Number:
Japanese Patent JPS5922148
Kind Code:
A
Abstract:

PURPOSE: To detect margins of a logical circuit, memory, etc., by providing plural clock supplying circuits, and supplying a marginless clock during a diagnosis.

CONSTITUTION: When an electric power is turned on, a processor 7 reads a power-on diagnostic program out of a control storage CS5 and starts executing it. A switching control circuit 8 selects a marginless clock signal supplying circuit 1 through a switching circuit 4 to supply the clock signal to a processor 7, CS5, RAM6, circuit 9 to be controlled, and the circuit 8. Consequently, when the execution of the diagnostic program is completed normally, the processor 7 sends a request to select a next clock signal to the circuit 8. The circuit 8 selects a marginless clock signal supplying circuit 2 and the diagnostic program is executed similarly. When the execution is completed normally, a diagnosis end signal is sent to the circuit 8. The circuit 8 selects a clock generating circuit 3 for normal operation and sends the signal as mentioned above to send a reset signal to the processor 7, making a return to the normal operation.


Inventors:
KATOU KEIICHI
Application Number:
JP13256782A
Publication Date:
February 04, 1984
Filing Date:
July 29, 1982
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F11/22; G06F1/04; G06F11/24; (IPC1-7): G06F1/04; G06F11/22
Attorney, Agent or Firm:
Koshiro Matsuoka