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Title:
POWER CONSUMPTION REDUCING CIRCUIT OF COMPUTER
Document Type and Number:
Japanese Patent JPS5979324
Kind Code:
A
Abstract:

PURPOSE: To reduce power consumption of a whole system remarkably by using a CPU provided with stand-by function and constituting a circuit so that the stand-by function acts alway when the CPU is waiting for key inputting.

CONSTITUTION: A CPU1 is provided with stand-by function and so constructed that it always holds a waiting mode by itself when waiting for key inputting, and releases the waiting mode using a key input signal when a key is pushed to input to an input port. When a HALT mode is used as a waiting mode, it is normally interruption is required, and interruption request signal is made from a keyboard output through an OR gate when the output of a keyboard 2 is given to the input port of the CPU1 and attains to HALT mode release input. Also, in case where a STOP mode is used, STOP mode release input is made from output of the keyboard 2 through the OR gate 3.


Inventors:
OOSAKI SUKETSUGU
Application Number:
JP18945482A
Publication Date:
May 08, 1984
Filing Date:
October 28, 1982
Export Citation:
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Assignee:
NIPPON DENKI HOME ELECTRONICS
International Classes:
H02J1/00; G06F1/32; G06F15/02; (IPC1-7): G06F1/00
Domestic Patent References:
JPS56152020A1981-11-25
Attorney, Agent or Firm:
Takeo Masuda