PURPOSE: To improve the circuit integration by constituting an input stage inverter with two insulation gate FETs so as to realize a high input impedance and decrease the chip area.

CONSTITUTION: An output of the input stage inverter connecting MOSFETs Q1, Q2 in series is given to MOSFETs Q3, Q4 and an inverter G8, its output is fed back to the FETQ4 and also to the FETQ3 viala G9. Since the FETQ2 is turned ON when an input signal IN is logical "1" and the FETQ1 is turned ON always in this constitution, the FETs Q3, Q4 are turned OFF and ON respectively. When the signal IN is inverted to 0, the FETs Q3, Q4 are turned ON and OFF respectively and a circuit threshold voltage VL of an ND1 is decided by the FETs Q1, Q2, Q3, Q4 are turned respectively ON, ON, OFF and ON and the circuit threshold voltage VH of the ND1 is decided by the FETs Q1, Q2, Q3. Different circuit threshold voltages VH, VL are given to the leading/trailing of the signal IN by changing the characteristic of each FET and the hysteresis width is VH-VL.