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Patent Searching and Data


Title:
ARRAY LIMIT INSPECTING DEVICE
Document Type and Number:
Japanese Patent JPS5818757
Kind Code:
A
Abstract:

PURPOSE: To compare the magnitude of bit fields with a limit value at every dimension, by directly representing the bit field in multidimension by assigning the bit field to addresses of each dimension against addresses to be accessed to an array composed of random access memories.

CONSTITUTION: In an array defining register 1 which defines the dimension of arrays, a bit field assigned to three-dimensional arrays (a), (b), and (c) is defined by combination of "0" and "1", and limit values to each dimension are stored in another register 2. When an array address signal 4 is inputted to access the array, the signal is compared with the limit value in the array limit register 2 at every dimension in accordance with the definition of the array defining register 1, and when the signal exceeds the inputted limit, an output signal is generated from a combination logical operation circuit 3 and an error detect signal 5.


Inventors:
OZAWA SUMIO
Application Number:
JP11696881A
Publication Date:
February 03, 1983
Filing Date:
July 24, 1981
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F11/28; G06F9/06; G06F11/00; (IPC1-7): G06F11/22
Attorney, Agent or Firm:
Toshio Nakao