Title:
CENTRAL ARITHMETIC PROCESSING CIRCUIT APPLICATION DEVICE
Document Type and Number:
Japanese Patent JPS6020243
Kind Code:
A
Abstract:
PURPOSE: To select the operation speed of the program suitable for the user, by providing the function which can vary the operation speed of the program.
CONSTITUTION: CPU1 reads the memory contents of the system ROM2 through the data bus 4. The clock signal needed for CPU1 to operate is generated by the clock occurrence circuit 7. The operation speed variable circuit 16 is installed between the CPU1 and clock occurrence circuit 7. The operation speed of CPU1 is varied freely by thinning the clock signal in accordance with the needs. This operation speed variable circuit 16 consists of the address identification circuit 12, operation speed setting circuit 13, delay signal occurrence circuit 14 and operation temporary stop circuit 15.
Inventors:
HIRAHATA SHIGERU
ITOU TAMOTSU
TATEISHI MICHIHIRO
ITOU TAMOTSU
TATEISHI MICHIHIRO
Application Number:
JP12770183A
Publication Date:
February 01, 1985
Filing Date:
July 15, 1983
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G06F9/30; G06F1/04; G06F1/08; (IPC1-7): G06F1/04; G06F9/30
Domestic Patent References:
| JPS59168548A | 1984-09-22 |
Attorney, Agent or Firm:
Namio Akio (2 outside)
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