PURPOSE: To attain detection of generation of erroneous counts, by providing a detection circuit which detects and compares polarity of input pulse synchronizing with rise and fall of gate signals.

CONSTITUTION: Gate signal 7 is converted into the 1st clock signal 16 through a monostable multivibrator 11a. Then, an FF13a becomes at a rise timing of the signal 16 such that when an input pulse string 6 is logic "1", logic "1" is obtained, and when it is logic "0", logic "0" is obtained. This condition is retained until a reset signal 18 arrives. Output of the FF13a becomes the 1st discrimination signal 19. In addition, a signal 7, whose polarity of logic "1" and "0" is inverted through an inverter 12, turns into an inverted gate signal 15 and into the 2nd clock signal 17 through a monostable multivibrator 11b. Next, an FF13a operates at a rise timing of a signal 17 such that the input pulse string is logic "1", logic "1" is obtained, and when it is logic "0", logic "0" is obtained. This condition is retained until the signal 18 arrives. Output of the FF13b a becomes the 2nd discrimination signal 20. An AND circuit 14 compares a signal 19 with 20 and sends a signal of logic "1" as a detected signal 21 only when both the signals are logic "1".