PURPOSE: To reduce the quantity of hardware by sharing part of a circuit to detect the overlap of addresss and the stored instruction confliction.

CONSTITUTION: When data of n-bit registers 1W3 are referred to nR1WnR3, respectively, equations I and II are used to detect the overlap of addresses and a stored instruction confliction S-1 CONF, respectively. In the arithmetic of the equiation I , the read and store addresses are supplied to registers nR1 and nR2 respectively together with the operation of multiplexers MX1 and MX2. In the arithmetic of the equation II, multiplexers MX1W5 are switched to output high- order (n-m) bits of nR3 and nR1, medium-order (m-m') bits of nR3 and nR1, high-order (n-m) bits of nR3 and the output of an adder AD2, and medium- order (m-m') bits of nR3 and the output of an adder AD3 to exclusive OR circuits EOR2, 3, 1 and 4, respectively.