PURPOSE: To obtain a frequency dividing circuit having the capacity for generating a frequency dividing output of one over an optional integral number with simple constitution by inputting an optional number of order of a logical output of DFFs connected in series to the DFF of the 1st stage.

CONSTITUTION: When the 3rd clock pulse CP is applied, outputs QB, QC of the DFF21B, 21C go to 1 and an output QND of an NAND circuit goes to 0. When the 4th clock pulse CP is applied, an output QA of the DFF21A goes to 0 and when the 5th clock pulse CP is applied, an output QB of the DFF21B goes to 0 and an output QND of an AND circuit 22 goes again to 1. The outputs QA, QB and QC of the DFF21A, 21B and 21C are an output of period 5T comprising 3T of 1 level and 2T of 0 level (T is the period of the clock pulse), i.e., a frequency dividing output having 1/5 of the clock pulse CP.