PURPOSE: To enable to limit the word length to the desired length without using any special processing step for a digital arithmetic circuit, by using a word length limiting circuit which limits the word length of data together with a word length deciding circuit.

CONSTITUTION: When the word length is limited to 12 bits with a 16-bit constitution of registers AR, BR and CR respectively, the information on the limitation of the word length to 12 bits is set to a word length deciding register WR. Then a logical arithmetic processing result of 16 bits obtained by a logical arithmetic part ALU is set to the register CR. When this processing result is transferred to a memory, etc. via a data bus BUS, the data word length of 16 bits of the register CR is limited to 12 bits by a word length limiting circuit WL and transferred. Thus the word length can be limited to the desired value without executing a word length limiting step instruction by setting the limited word length temporarily to the register WR.