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Title:
TIME DIVISION MULTIPLYING CIRCUIT
Document Type and Number:
Japanese Patent JPS59133673
Kind Code:
A
Abstract:

PURPOSE: To make it unnecessary to combine the absolute value of an input signal on the outside of an IC and improve operation precision by dividing the voltage of an input signal inside the IC to generate the earth potential of an integrator.

CONSTITUTION: Input signals Y and -Y supplied through MOS transfer gates 3a and 3b are given to the inverted input terminal of an operational amplifier 11 constituting an integrator 1 through a resistance Ri. A pair of depletion type MOSFETs Q1 and Q2 are connected in series between wirings l1 and l2 connecting input terminals 5a and 5b and transfer gates 3a and 3b. These FETs Q1 and Q2 constitute a pair of resistance elements, and signals Y and -Y voltage divided. Consequently, since the wirings l1 and l2 are adjusted to supply the potential in an intermediate level due to voltage division to the integrator 1 as the earth potential, it is unnecessary to combine the troublesome absolute values of input signals on the outside of the IC, and the precision of the earth potential is enhanced.


Inventors:
TORII SHIYUUICHI
OGAWA KAZUYOSHI
Application Number:
JP726883A
Publication Date:
August 01, 1984
Filing Date:
January 21, 1983
Export Citation:
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Assignee:
HITACHI LTD
HITACHI MICROCUMPUTER ENG
International Classes:
G06G7/161; G06G7/16; (IPC1-7): G06G7/16
Attorney, Agent or Firm:
Akio Takahashi



 
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