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Title:
CLOCK SYNCHRONIZING SYSTEM
Document Type and Number:
Japanese Patent JPS60109345
Kind Code:
A
Abstract:

PURPOSE: To improve the using efficiency of a burst signal by fixing the clock synchronization by plural burst signals transmitted from the same earth station and eliminating the need for the clock reproducing code contained in the burst signal.

CONSTITUTION: A burst clock reproducing circuit 32 reproduces a burst clock 33 to a reception burst signal 31 and compares the phase of a master clock 44 of the own station with the phase of the clock 33 at the latter half part of the signal 31. The mean value of plural phase difference signals thus obtained are stored by a fixed latest number for plural burst signals. An identification clock 49 of the signal 31 is produced by meand of the mean value of the stored phase difference information and then supplied to a discriminating circuit 57. The synchronization of this clock is performed by a clock synchronization detecting circuit 59. Then a reception signal 58 is fetched by a clock synchronization fixing signal 60.


Inventors:
ATSUGI GAKUO
SHIYOUMURA TATSUROU
SAMEJIMA SHIYUUICHI
Application Number:
JP21593983A
Publication Date:
June 14, 1985
Filing Date:
November 18, 1983
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H04B7/155; H04B7/212; H04L7/027; H04L7/033; H04L7/04; H04L7/10; H04L7/08; (IPC1-7): H04B7/155
Domestic Patent References:
JPS5636249A1981-04-09
Attorney, Agent or Firm:
Keiichi Yamamoto



 
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