PURPOSE: To obtain a logical gate circuit at a high speed with low power consumption, which consists of a field effect transistor and a bipolar transistor, by providing a p type field effect transistor as a discharge bus of a storage charge between the base of the first npn transistor and an output terminal.
CONSTITUTION: As for NMOSs 21, 22, the respective drains are connected in common to an output, the respective sources are connected in common to the base of the second npn, and the respective gates are connected to the first input A and the second input B. In case both inputs A, B are switched to a low level from a high level, NMOSs 21, 22 are turned off, and an npn 32 also off. On the other hand, both PMOSs 11, 12 are turned on, a base current is supplied to an npn 31 from power source +V, the npn 31 is turned on, and an output is switched to a high level from a low level. Accordingly, when the base potential of the npn 31 is below a threshold voltage of a PMOS51, the PMOS51 is remained to off state, currents flowing through the PMOSs 11, 12 are all used for charging of a base area of the npn 31, and the npn 31 is turned on quickly.
IWAMURA MASAHIRO
NISHIO YOUJI
| JPS5979641A | 1984-05-08 |