PURPOSE: To facilitate easy address control of each memory in the reduction and rotary read modes by using (n) bits as common bits and the remaining (m) bits as those which decide the positions of data respectively among address inputs to be fed to a memory.

CONSTITUTION: Data are divided into blocks every (N×M) bits, where N and M equal to ≥2 integers. Then (n) bits of address inputs to be fed to a memory circuit 11 are used as those which define blocks. At the same time, the remaining (m) bits are used as those which define the data positions within those blocks. In a write mode of data the input data are converted into parallel data for each 4 bits by an S/P shift register 8 and then written to addresses corresponding to values n, m1Wm4 supplied from address conversion circuits 5 and 6 by the circuit 11. In this case, the value of (n) of each memory is used in common within a block, and the value of (m) is used to define an address when the varied data is written to a memory. As a result, the address control is facilitated when data are read out with reduction and revolution respectively.