Title:
SEMICONDUCTOR SUBSTRATE
Document Type and Number:
Japanese Patent JPS59159558
Kind Code:
A
Abstract:
PURPOSE: To increase the degree of freedom for circuit design and thus optimize the arrangement of elements by regularly forming unit patterns consisting of element isolation diffused regions.
CONSTITUTION: The semiconductor substrate has the unit patterns 10 consisting of three longitudinally long element isolation diffused regions 11 having N+ buried layers 12 and four transversely long ones 13 having N+ buried layers 14 regularly arranged over the entire surface. The region 13 has the N+ buried layer 14 at the bottom. The resistor formed on said substrate can be freely designed without being restricted by the pattern of the regions 13 by using a thin film resistor. The transistor is formed on the region 13.
Inventors:
AMANO TAKASHI
Application Number:
JP3343883A
Publication Date:
September 10, 1984
Filing Date:
March 01, 1983
Export Citation:
Assignee:
TOSHIBA KK
International Classes:
H01L21/822; H01L21/82; H01L27/02; H01L27/04; H01L27/118; (IPC1-7): H01L21/76; H01L21/82; H01L27/04
Domestic Patent References:
| JPS5125085A | 1976-03-01 | |||
| JP46036825A | ||||
| JPS4818036A |
Attorney, Agent or Firm:
Kazuo Sato