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Patent Searching and Data


Title:
MICROPROCESSOR ANALYZER
Document Type and Number:
Japanese Patent JPS5819962
Kind Code:
A
Abstract:

PURPOSE: To reduce the repetition of debugging, by providing a correction management memory, where the log of corrections is stored, while facilitate the respons to a source list.

CONSTITUTION: Contents of a program PRG incorporated in a device 36 to be tested are fetched into a RAM32 for emulation through an externak interface circuit. After that, the device 36 is operated by the PRG stored in the RAM32. In this case, a command signal is inputted from a keyboard 30 to operate the device 36 in every several steps. In respect to the operation defect in this operation, the PRG is corrected manually from the keyboard 30. A PRG list for correction is displayed on a CRT35 by a controller 31. Consequently, the operator corrects the PRG while watching the PRG sequence displayed on the CRT35. At this time, the controller 31 stores corrected addresses of the PRG in a correction management memory 33.


Inventors:
SAKURAI KAZUAKI
UCHIDA HIROTAKA
Application Number:
JP11864081A
Publication Date:
February 05, 1983
Filing Date:
July 29, 1981
Export Citation:
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Assignee:
YOKOGAWA ELECTRIC WORKS LTD
International Classes:
G06F11/28; G06F9/06; G06F11/36; (IPC1-7): G06F11/28
Domestic Patent References:
JPS50139639A1975-11-08
JPS5676853A1981-06-24
JPS55163697A1980-12-19
Attorney, Agent or Firm:
Shinsuke Ozawa