Title:
EROR DETECTING METHOD
Document Type and Number:
Japanese Patent JPS601677
Kind Code:
A
Abstract:
PURPOSE:To detect assuredly an error of a data word by considering all words as errors only in case no correct data word consists in a data block containing data words which are simultaneously detected as erroneous by error detection codes of plural different series. CONSTITUTION:A data block formed with a prescribed number of words D1, D2-, error check bit codes P and Q of P and Q series different from the blocks of said data words, a cyclic redundancy check code C of the same series as said data words, etc. Then flags F1-F4 for codes P and Q of words which are simultaneously decided erroneous by the code P and Q are all set at ''1''. Other words of this block are also processed in the same way. If >=1 correct words are not included with a flag of ''0'' in the words D1, F2-, the words D1, D2- of the block are all considered as errors. It is prevented that all words including correct ones are regarded as errors. In such a way, a word error can be detected assuredly.
Inventors:
HIMENO TAKUJI
Application Number:
JP10886883A
Publication Date:
January 07, 1985
Filing Date:
June 17, 1983
Export Citation:
Assignee:
SONY CORP
International Classes:
G11B20/18; (IPC1-7): G11B20/18
Attorney, Agent or Firm:
Sada Ito (1 person outside)
Next Patent: JPS601678