PURPOSE: To obtain a detecting circuit which is usable without any adjustment by connecting plurally a delay circuit which has an optional delay time in series, and inputting a clock pulse to the top delay circuit and ORing outputs of the respective delay circuits.

CONSTITUTION: Plural delay circuits each having an optional delay time are connected in series, and the clock pulse is inputted to the top delay circuit. For example, delay circuits DL1WDL3 hve delay times T1WT3, and TC<TW+T1+ T2+T3, where TW is the width of the clock pulse and TC is the clock time. Then, the clock (a) is delayed by the time T1 through the delay circuit DL1 to generate a clock (b), which is delayed successively to obtain a clock (d) as the output of the delay circuit DL3. When the clock pulse is normal, the outut of an OR gate OR is held at "H", and when the clock 1 of the clock (a) is disappeared owing to the break of a clock, the output of the OR gate OR is held at "L", thus detecting the clock break.