PURPOSE: To obtain a device, which operates at high speed and power consumption thereof is low, by selectively forming single crystal and polycrystalline layers onto one conductive type Si substrate through an SiO2 film, shaping a gate region at the predetermined position of the single crystal layer and molding source-drain to a section except the region.

CONSTITUTION: The SiO2 thin-film 12 of the <100> face of a P type Si substrate 11 and a P- type single crystal 13 and a polycrystalline 14 are formed in epitaxial shape, and an SiO2 15 and poly Si 16 through a CVD method are laminated. The layers 16, 15 are removed selectively, and the gate oxide film 15 and the gate electrode 16 are formed. N type source-drain 18, 19 are shaped through ion implantation, and thermally treated. The ion implantation layer 19 in the poly Si 14 spreads over the whole layer 14, the depth of the junction of the layer 18 is deep, and the depth of the junction of the layer 19 is deeply formed in a section separating from the gate region. Accordingly, since a short channel effect is prevented and the SiO2 12 is held between the N layer 19 and the substrate 11, the parasitic capacitance of the source-drain is reduced, and the FED, which operates at high speed and power consumption thereof is low, is obtained.