PURPOSE: To improve environmental resistance and to simplify its constitution by inputting the output of a specific logical gate to which a resolver output is shaped and inputted and the output of the 2nd low-order bit of a counter which synchronize with clock pulses to an FF, and counting its output.

CONSTITUTION: The high-order ten bits of a 12-bit counter 2 connected to an astable multivibrator 1 is inputted to D/A converters 4a and 4b through a ROM 3, and its output is applied to stator windings 5a and 5b of a resolver 5, whose rotary winding 5c is connected to an AND gate 7 through a pulse shaping circuit 6. On the other hand, the output of an exclusive OR circuit 8 to which the least significant digit bits of the astable multivibrator 1 and counter 2 are supplied is inputted to the gate 7, whose output is inputted as a clock input to a D.FF9 while the 2nd bit output of the counter 2 from the least significant digit bit is inputted as a data input; and the output of the FF9 is counted by a counter 10.