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Title:
PEAK VALUE VOLTAGE DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JPS5822964
Kind Code:
A
Abstract:

PURPOSE: To easily detect a peak value of input voltage, by storing and holding threshold voltage corresponding to an input signal level applied to the drain, and using a non-volatile memory of an MOS structure, whose storage is updated by an input signal of a higher level.

CONSTITUTION: Input voltage from a sensor, etc. is applied to a waveform shaping circuit 11, and the circuit 11 is constituted so as to be fetched by switching only an input signal in the positive direction or only an input signal in the negative direction against the input voltage. Negative voltage is applied as an output of the circuit 11 to a memory circuit 12 through a changeover switch (SW) 1. On the circuit 12, transistor (TR1W7) for controlling the write and read-out against a non-volatile memory M1 of a P channel MOS structure, and gate circuits G1, G2 are provided. To the memory M1, an output of the circuit 11 is provided through the TR 2, and it is updated only when an erase signal E has been applied through the TR 1. A signal read out through the TR 7 is capable of obtaining peak value voltage corresponding to input voltage through an output detecting circuit 14, and the SW 1.


Inventors:
KUTSUYAMA HIROSHI
YAMADA MAKOTO
Application Number:
JP12283581A
Publication Date:
February 10, 1983
Filing Date:
August 04, 1981
Export Citation:
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Assignee:
SANYO ELECTRIC CO
International Classes:
G01R19/04; (IPC1-7): G01R19/04
Attorney, Agent or Firm:
Maruyama Kizo



 
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