PURPOSE: To supply a clock which has a longer period than a normal clock, by adding a few circuits to a circuit which supplies a single shot clock to a system.

CONSTITUTION: When an indication signal for time-lagged clock supply is supplied to a terminal bS, an FF4 is set and its output B is held at "1". At the same time, a temporary clock stop signal aS is also supplied, the output A of an FF1 is also held at "1". Once the output B goes up to "1", a start key CST signal is generated through a service processor SVP to obtain a period wherein a clock stop reset condition signal aR is held at "1" and a terminal A is held at "0", and only one pulse is applied to a system clock terminal when an oscillation pulse of a clock oscillator CLK is generated during the period. When a condition signal bR for time-lagged clock resetting is obtained, the FF4 is reset and while a terminal B is held at "0", a terminal A is also held at "0", performing resetting to an initial state.