PURPOSE: To make high speed operation and low standby power consumption compatible by bringing a threshold potential of one of P channel or N channel transistor (TR) to a potential different depending on the normal operation and standby state.
CONSTITUTION: In connecting a substrate potential internal generating circuit 11 to an N channel TR 10 in an inverter circuit, the substrate potential internal generating circuit 11 is thrown to the position of a switch (a) in the normal operating state, the substrate potential of the N channel TR 10 is brought to the common potential. When the standby control flip-flop is set, the oscillating circuit is stopped, a RAM data is stored and the mode is transmitted to the standby state, then the substrate potential generating circuit 11 throws the switch to the position (b). The substrate potential of the N channel TR 10 is lowered by Vs than the normal operation, the current OFF characteristic of the N channel TR is improved than that at the normal operation and low power consumption is realized.
JPH04139694 | DESIGNING METHOD FOR MULTIPORT STATIC RAM |
JP2012043502 | SEMICONDUCTOR MEMORY |
JPS5472691A | 1979-06-11 | |||
JPS55118666A | 1980-09-11 |