PURPOSE: To shorten the test time by providing a circuit presetting directly a segment shift register and setting an optional data obtained by an instruction data bus of the said circuit to a register to reduce the test pattern length.

CONSTITUTION: In checking the operation of a segment shift register 1, a preset circuit 4 is divided at first into K-block and an accumulator 9 accesses one block in the K-block. An optional data is set to one block via an n-bit line of the instruction data bus 14. Then a data in the register 1 is transferred to a parallel register 2 and the segment is tested from the propriety of the output of the segment buffer 3. After an optional data is preset at a test terminal 6 for the confirmation of the shift operation of the register 1, the level of the terminal 6 is brought into "0" to restore the mode from the test mode to the normal mode to check the shift operation of the register 1 thereby shortening the test time.