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Title:
PEAK HOLD CIRCUIT
Document Type and Number:
Japanese Patent JPS604866
Kind Code:
A
Abstract:

PURPOSE: To make it possible to obtain an extremely long peak hold time to a rising time, by using a diode as the gate bias element of an electric field effect transistor.

CONSTITUTION: When a pulse signal to be modulated is applied, a detection diode 3 is brought to a continuity state and detection voltage detected by the diode 3 is charged in a rising peak hold capacitor 4. The charged voltage charged in the capacitor 4 is discharged while elapsing a peak hold time by the leak currents of the detection diode 13 and a gate bias diode 11 and the gate current of an electric field effect transistor 7. The ratio of a rising time and the peak hold time is determined by the ratio of the continuity impedance of the diode 3 and the leak impedance and the gate impedance of the diodes 3, 11. A falling time becomes long 100 times as compared with the rising time, an extremely long peak hold time can be obtained.


Inventors:
SUGIMOTO ETSUO
Application Number:
JP11458783A
Publication Date:
January 11, 1985
Filing Date:
June 23, 1983
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
G01R19/04; H03K5/1532; H03K6/00; (IPC1-7): G01R19/04
Attorney, Agent or Firm:
Masuo Oiwa



 
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