PURPOSE: To generate assuredly clock pulses with a simple constitution, by generating a clock pulse which increases its cycle every prescribed N pulses from a clock generating circuit and therefore decreasing the capacity of a clock pulse counter.

CONSTITUTION: The 1st counter 1 is reset with an initial reset signal A, and the counter 1 counts successively reference clock signals B and then delivers the count value of binary codes from output terminals Q1∼Q128. This count value is selected by a selector 2, and clock pulses C are delivered. These pulses C are counted by the 2nd counter 3, and an output signal D is delivered when the count value of the pulses C reaches a prescribed value N. An OR is obtained between signals D and A by an OR gate 4, and the outputs of the gate 4 are counted by the 3rd counter 5. The count value of the counter 5 is applied to the selector 2 as a selection signal. Then a clock pulse is generated having its cycle increasing every prescribed N pulses. Thus the constitution is simplified for a clock pulse generating circuit.