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Title:
BI-DIRECTION SHIFT REGISTER
Document Type and Number:
Japanese Patent JPH04134798
Kind Code:
A
Abstract:

PURPOSE: To eliminate the difference of set up and hold time of data by making a 1st bit and a nth bit of a bi-directional flip-flop circuit of (n) numbers to be adjacent, and arranging them on a signal input terminal side.

CONSTITUTION: The order of the layout arrangement of the bi-directional flip- flop circuit of 1W10 is, for example, the 1st bit, 10th bit, 2nd bit, 9th bit, ...5th bit, 6th bit. The set-up and hold time of the data in such a case is decided by the input timing of the shift clock input terminal 13 and the DATA input terminal 11 of the bi-direction flip-flop circuit 1 of the 1st bit. Also, the output delay time is decided by the input timing of the shift clock input terminal 13 and the input/output terminal 11 of the 10th bit bi-direction flip-flop circuit 10. Thus, the set-up and hold time and the delay time of the data at the time of left shift and right shift can be made the same.


Inventors:
NAKAKARUMAI SUSUMU
Application Number:
JP25784090A
Publication Date:
May 08, 1992
Filing Date:
September 26, 1990
Export Citation:
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Assignee:
KANSAI NIPPON ELECTRIC
International Classes:
G11C19/00; (IPC1-7): G11C19/00
Domestic Patent References:
JPS6316500A1988-01-23